Overview:

The circuit outputs an adjustable 0-10V linear ramp (now set at 7Hz) with a sync output that changes at the transitions between rising and falling ramps.  The ramp is used to drive piezo disks on a spectrometer (through a high voltage amplifier with a gain of about 20, need a few hundred volts to move the PZs enough).  The HV amp also has DC offset adjustments.  Current settings are: Rise time 100ms, fall time 40ms (slower than the fall time shown on the scope pic).

How it works:

An integrator produces a linear ramp when charged/discharged with a constant current.  U3A with the feedback caps (C9-11) form the integrator.  U2 is a CMOS switch that switches between two inputs tied to different voltages (one positive, one negative).  U3A keeps the negative input at ground so a fixed voltage across R3 & R5 or R4 & R6 provides a constant current in or out of the integrator.  U1 is a 5V ref and the wiper on R1 sets the voltage difference between the false ground and the top and bottom of the 5V ref.  Adjusting R5 & R6 and shorting jumper J2 (increasing the capacitance) allows the rise/fall time and frequency to be changed.

U4 compares the output of the integrator to the false ground and the high side of the 5V ref.  When the integrator ramp increases past the high side of the 5V ref U4A goes high setting U5A (a flip-flop).  Q bar is now low and flips the CMOS switch to the S1 input (pin 2).  This lets current flow from the high side of the Vref (through R3 & R5) to the integrator which causes the integrator to ramp down.  When the integrator output goes below ground U4B goes high resetting U5A.  Q bar is now high and flips the CMOS switch to the S2 input (pin 8).  This lets current flow from the integrator to the low side of the 5V ref (through R4 & R6) which causes the integrator to ramp up.

U3C buffers the false ground.  R13 adjusts the amplitude of the ramp.  R13 & C17 take out any high frequency noise.  U3D buffers and amplifies the final output.  The existing board has a 10K & 1K resistor instead of the pot (R1).  This gives the voltages shown on the schematic (with reference to the false ground).  With a 12V wall wart these settings allow for a 0-10V ramp.  Note: The sync output goes from ground to 11.55V.  This is not a TTL output.  We use it for triggering a scope.  U3 is a rail-to-rail I/O op-amp.  The outputs can get within 100mv or so of the rails at low output current.  R11 & R16 hopefully keep bad things from happening if the outputs are shorted or connected to the wrong BNC.

I used a 12V wall wart because it's cheap and doesn't take up much space (and having a PS in such a small box with an XFMR and leaking magnetic field could induce unwanted noise).  D1, C1, & C2 remove most of the hight frequency switching noise (D1 is a high speed signal diode).  Each IC is decoupled with LC filters to further smooth the power supply.

Note: The integrator was noticeably non-linear with  2.2uF and 10uF ceramic caps (805 size).  I had some 0.1uf/16V 1210 size metalized PPS caps that show now DC bias (i.e. change in capacitance with applied DC voltage).  Once I replace the ceramic caps with the PPS caps the ramp was very linear.