;**********************************************************************

; timer and watchdog set up
tmrset
	; use prescaler with watchdog timer 0 (set for divide by 128)
	bsf	STATUS,RP0		; bank 1
	bcf	OPTION_REG,T0CS		; TMR0 uses FOSC/4
	bcf	OPTION_REG,T0SE		; TMR0 increments on rising edge
	bsf	OPTION_REG,PSA		; use prescaler with watch dog timer
	bsf	OPTION_REG,PS2		; set MSB of prescaler
	bsf	OPTION_REG,PS1		; set middle bit of prescaler
	bsf	OPTION_REG,PS0		; set LSB of prescaler
	bcf	STATUS,RP0		; bank 0

	; use prescaler with timer 1 (set for divide by 8 - timer1 ON)
	; timer1 is used for the delay between pulses to the stepper motor
	bsf	T1CON,T1CKPS1		; set MSB of prescaler
	bsf	T1CON,T1CKPS0		; set LSB of prescaler
	bcf	T1CON,T1OSCEN		; inverter off (save power)
	bsf	T1CON,T1SYNC		; don't sync w/external clock
	bcf	T1CON,TMR1CS		; use FOSC/4 for clock input
	bsf	T1CON,TMR1ON		; timer 1 ON

	; postscaler /16, prescaler /16, timer2  ON)
	; total delay should be 1uS * 16 * 16 * 20 = ~5ms W/4MHz clock
	bsf	T2CON,TOUTPS3		; set MSB of postscaler
	bsf	T2CON,TOUTPS2		; set bit 2 of postscaler
	bsf	T2CON,TOUTPS1		; set bit 1 of postscaler
	bsf	T2CON,TOUTPS0		; set LSB of postscaler
	bsf	T2CON,TMR2ON		; timer 2 ON
	bsf	T2CON,T2CKPS1		; set MSB of prescaler
	bsf	T2CON,T2CKPS0		; set LSB of prescaler
	bsf	STATUS,RP0		; bank 1
	movlw	d'20'			; roll-over every 20 clock cycles
	movwf	PR2			; load delay register
	bcf	STATUS,RP0		; bank 0
	clrf	BYTCNT			; zero byte counter
	return

;**********************************************************************

