Linear 3.3V LED Driver We needed to get a lot of light at around 630nm because that's where the windows on a DAC (diamond anvil cell) they're trying to image is mostly transparent. This LED was chosen because it's close to the right wavelength and puts out enough light. I ordered the LED mounted on a star board to make mounting to a heatsink easier. I also ordered heatsink made for the star board (but I had to tap the holes on the heatsink to mount the LED and PCB). I got the 2" long heatsink to keep it a bit cooler as this LED looses about 10% efficiency for every 12-13C increase in temperature. We also prefer not to have a fan on the heatsink as it may cause vibrations on the optical table. Circuit description The LED has a forward voltage of about 2.7V at 1A. I decided to use a 3.3V wall wart and linear regulation rather than using a switching supply to control the current. The efficiency isn't too bad. At 1A, 0.6V is dropped across the sense resistor and power FET. The remaining 2.7V of the 3.3V power supply is across the LED for an efficiency of 82%. The heat lost in the sense resistor and FET is dissipated in a small heatsink as opposed using the LED heatsink so as not to further heat up the LED. The op-amp measures the voltage across the 0.3 ohm sense resistor, compares it to the current set point, and amplifies the difference with a gain of 100. The set point voltage is set with a potentiometer (R3). R1, R2, & R3 set the max voltage across the pot to just under 0.3V. With the 0.3 ohm current sense resistor the max current is about 0.9A. It turns out that 0.5A provides plenty of light to see inside the DAC. The error signal (100X the difference between the desired current and actual current) drives the gate of a low Vgs_threshold power FET. Since we're using a 3.3V power supply the FET can't require too high of a gate voltage to drive 1A through the LED. The IRL3103PBF has a 1V threshold voltage. The op-amp also has rail-to-rail outputs and can drive the output to within 20mV of the 3.3V power supply. Worst case (at 1A) we have a 0.3V drop across the sense resistor leaving Vgs=3V. The FET datasheet shows that even when Vgs=2.7V the FET would let 4A flow with Vds=0.3V (a good safety margin since we only need 1A). The input capacitance of the FET is about 1.7nf. With the 100K gate resistor the corner frequency of the FET response is about 1KHz. The setpoint pot & filter cap (R3 and C2) has a corner frequency of 3KHz or higher. The op-amp has a GBW of 2.2MHz and a gain of 100 putting it's corner frequency around 22KHz. The FET responds much slower than the amplifier and nothing oscillates. The voltage across the FET, the sense resistor, and gate voltage all look flat (i.e. DC, assuming one isn't adjusting the current). The caps provide decoupling to smooth the switching power supply ripple. Smaller caps respond faster (usually lower ESL & ESR) than larger caps so different size caps are paralleled to cover a wider frequency range. The op amp also has a ferrite bead (inductor) before its decoupling caps to further smooth the power rail to the op-amp.